Custom
Connector Signal Integrity Expertise for a Broad Range of
Applications
Pre Layout Design Analysis
Pre-layout simulation allows us to predict and eliminate
signal integrity problems early, allowing us to proactively
constrain routing, plan stackups, and optimize clock, critical
signal topologies and terminations prior to board layout.
Pre-layout simulation is the ideal way to “get it
right” the first time.
We can include the Test Socket models and conduct and interconnect
scenarios with different vendors sockets over different
speeds and voltages and compare data eyes.
Post Layout Design Analysis
Post-layout signal integrity simulation allows us to analyze
signal integrity and timing at three important stages: following
part placement in your PCB layout system, after critical
net routing, and after detailed routing of an entire PC
Board:
Batch simulation automatically scans large numbers of
nets on and entire board flagging SI and EMC hot spots
Interactive analysis takes you to the next level, simulating
batch analysis-identified trouble spots
Quick Terminators allow new termination components to
be inserted on-the-fly, enabling real-time analysis
Our analysis accurately predicts crosstalk waveforms for
any trace topology and IC placement, also showing the specific
board cross-sections in violation of crosstalk thresholds
Compatible PCB Layout Systems
Mentor Graphics PADS Layout, Expedition and Board Station
Cadence Allegro, SPECCTRA and OrCad Layout
Altium Protel and P-CAD
Intercept Pantheon
Zuken CADStar Visula and CR3000/5000 or Board Designer
Other benefits of our consulting services
Accurate modeling of lossy transmission line effects,
including skin effects and dielectric loss
Analyze inter-symbol interference in multi-gigabit signals,
including random jitter, eye diagrams and eye masks to
define keep-out regions
Simulate with spice or IBIS models
Advanced via modeling
Differential signal simulation and analysis, including
impedance planning and optimization of differential terminations
Optimization of termination strategies, including series
termination, parallel, parallel AC and differential
Provides an early look at likely EMC failures, including
both radiation and trace current analysis
If you would like to speak with a
design specialist about your interconnect requirements,
contact us for
a no obligation discovery meeting. We look forward to hearing
from you.
US Patent
#s 6,787,709, 6,909,056, 7,019,222, 7,126,062.
Other US & Foreign Patents Pending.